The present invention relates generally to the fabrication of spacers on the sides of a gate structure of a semiconductor device, and more particularly, to methods for controlling spacer oxide loss.
The advent of micro-miniaturization, or the ability to fabricate semiconductor devices with sub-micron features, has resulted in improved device performance as well as decreases in processing costs. Smaller device features allow reductions in performance degrading parasitic junction capacitances to be realized. In addition, a greater number of smaller semiconductor chips comprised with sub-micron features, but still exhibiting device densities equal to, or greater than, counterpart semiconductor chips fabricated with larger features, can be obtained from a specific size substrate thus reducing the processing cost for an individual semiconductor chip. However, the trend to micro-miniaturization can place stringent demands on specific semiconductor elements. For example, for sub-0.13 um technology, gate spacers formed on the sides of a gate structure can be less than 700 Angstroms in thickness and typically, a thin liner oxide layer is formed underlying the gate spacers and interposed between the gate spacers and the gate structure and the gate spacers and the substrate. The number of times during a process a semiconductor device is subjected to an hydrofluoric (HF) containing wet etch procedure, can result in severe undercutting of the thin liner oxide layer at a bottom and a top portion thereof. The undercut can result in yield loss due to gate to substrate shorts or leakages.
FIGS. 1–3 illustrate the problem of undercut where the occurrence of the undercut is in a layer of liner oxide that is created between a gate spacer and a gate structure. As an example, FIG. 1 shows a cross-sectional view of a partial formation of a conventional CMOS device. The CMOS device created over the surface of a substrate 2 may include: a layer of gate material of the gate structure 6, typically comprising polysilicon; a gate insulator layer 4 formed over the surface of substrate 2; a liner layer 8, deposited over the surface of substrate 2, including the surface of the gate structure 6; and a layer of gate spacer material 10 deposited over the surface of liner layer 8. These structures and the processes for their formation are conventional.
FIG. 2 is a view of the structure of FIG. 1 after the layer of gate spacer material 10 has been etched, stopping on liner layer 8. Also shown are gate spacers 7 created on the sidewalls of the gate structure 6. After the spacers 7 have been created, the liner layer 8 will need to be removed from the surface of substrate 2 where the surface of liner layer 8 is exposed. This process of removal may be performed by etching liner layer 8 using a wet etch procedure comprising an HF solution.
The results of this etch are shown in cross section in FIG. 3. Specifically highlighted in the cross section of FIG. 3 are undercut regions 9 which are the regions where the etched layer of liner layer 8 is attacked by the etch to the point where the etch proceeds underneath the gate spacers 7, resulting in loss of liner layer 8 in the interface between the gate spacers 7 and the gate structure 6 and in the interface between the gate spacers 7 and the substrate 2. Due to the loss of liner layer 8 in these undercut regions 9, device isolation and device performance are negatively affected.
Accordingly, what is needed in the art is a method of manufacture thereof that addresses the above-discussed issues.